Study

Computing

Computer Architecture 1R

  • Class 60
  • Practice 18
  • Independent work 102
Total 180

Course title

Computer Architecture 1R

Lecture type

Obligatory

Course code

183393

Semester

3

ECTS

6

Lecturers and associates

Course objectives

Overview and history of computer architecture; Multiple representations/layers of interpretation (hardware is just another layer); Bits, bytes, and words; Numeric data representation and number bases; Fixed- and floating-point systems; Signed and twos-complement representations; Representation of non-numeric data (character codes, graphical data); Representation of records and arrays.
Basic organization of the von Neumann machine; Control unit; Instruction fetch, decode, and execution; Instruction sets and types (data manipulation, control, I/O); Registers; Register transfer notation.
Assembly/machine language programming; Instruction formats; Addressing modes.
Assembly/machine language programming.
Assembly/machine language programming; Subroutine call and return mechanisms.
I/O and interrupts; I/O fundamentals (handshaking, buffering, programmed I/O, interrupt-driven I/O); Interrupt structures (vectored and prioritized, interrupt acknowledgment).
External storage, physical organization, and drives; Buses: bus protocols, arbitration, direct-memory access (DMA).
Midterm exam.
Control unit; Instruction fetch, decode, and execution; Instruction sets and types (data manipulation, control, I/O); Instruction formats; Addressing modes.
Assembly/machine language programming.
I/O and interrupts; I/O fundamentals (handshaking, buffering, programmed I/O, interrupt-driven I/O); Interrupt structures (vectored and prioritized, interrupt acknowledgment).
Main memory organization and operations; Buses: bus protocols, arbitration, direct-memory access (DMA).
Implementation of simple datapaths (including instruction pipelining, hazard detection, and resolution).
Storage systems and their technology; Memory hierarchy (importance of temporal and spatial locality); Main memory organization and operations; Latency, cycle time, bandwidth, and interleaving.
Final exam.

Prerequisites for:

  1. Computer Architecture 2
  2. Automation Practicum
  3. Project
  4. Embedded Systems

Required reading

Mario Kovač (.), Arhitektura računala (knjiga),
Mario Kovač, Danko Basch (.), Rukopisi s predavanja,
Danko Basch, Martin Žagar, Branko Mihaljević, Marin Orlić, Josip Knezović, Ivana Bosnić, Daniel Hofman, Mario Kovač (.), Zbirka programskih zadataka za procesor FRISC,
Martin Žagar, Josip Knezović, Ivana Bosnić, Mario Kovač (.), Zbirka programskih zadataka za procesor ARM 7

Minimal learning outcomes

  • List the main parts of processors and computers
  • Explain how processors execute instructions
  • Explain the function of the main parts of a processor
  • Solve simple programming problems in assembly language
  • Explain the interfacing and communication between processor, memoy, and IO units
  • Solve simple problems of communication between processor and IO units
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