Study

Computing

Computer Architecture 2

  • Class 60
  • Practice 8
  • Independent work 82
Total 150

Course title

Computer Architecture 2

Lecture type

Elective

Course code

183428

Semester

5

ECTS

5

Lecturers and associates

Course objectives

Control unit (hardwired realization vs. microprogrammed realization).
Control unit (hardwired realization vs. microprogrammed realization).
Control unit (hardwired realization vs. microprogrammed realization).
Control unit (hardwired realization vs. microprogrammed realization).
Heap vs. static vs. stack vs. code segments.
Cache memories (address mapping, block size, replacement and store policy).
Cache memories (address mapping, block size, replacement and store policy).
Midterm exam.
Instruction pipelining.
Introduction to instruction-level parallelism (ILP).
Superscalar architecture.
Virtual memory (page table, TLB).
Shared memory multiprocessors/multicore organization; Introduction to SIMD vs. MIMD and the Flynn Taxonomy; Multicore and manycore systems.
Shared multiprocessor memory systems and memory consistency; Vector processors and GPUs; Hardware support for multithreading.
Final exam.

Required reading

(.), S. RIbarić. Građa računala, Arhitektura i organizacija računarskih sustava,
(.), D. A. Patterson J. L. Hennessy. Computer Organization Design

Minimal learning outcomes

  • Distinguish the roles of major components of a computer including CPU, memory, buses and I/O devices.
  • Predict activity on the memory bus of a simple procesor, as a consequence of execution of short machine code snippets
  • Demonstrate the implementation of simple instructions at the logic level
  • Summarize design principles of instruction set architectures RISC and x86
  • Solve small-scale problems by complementing C with assembly
  • Summarize the organization of superscalar processors with dynamic pipeline scheduling
  • Illustrate stages of physical address generation in presence of caches and virtual memory
  • Explain the implementation of coarse-grained parallelism on multi-core and multi-processor computers
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