Study

Computing

Tools for Digital Design

  • Class 30
  • Practice 12
  • Independent work 108
Total 150

Course title

Tools for Digital Design

Lecture type

Elective

Course code

183417

Semester

5

ECTS

5

Lecturers and associates

Course objectives

Principles; System level design.
Language elements.
Behavioral model; Language elements.
Register transfer level (RTL) model; Language elements.
Language elements; Practical examples in VHDL and Verilog.
Code structure and organization; Practical examples in VHDL and Verilog.
Practical examples in VHDL and Verilog; Test bench; Functional simulation.
Midterm exam.
Measures of complexity; Implementation platforms ASICS, FPGA, CPLD.
Computer-aided design tools that process hardware and architectural representations; Implementation platforms ASICS, FPGA, CPLD.
Computer-aided design tools that process hardware and architectural representations; Generic and vendor agnostic design.
Practical examples in VHDL and Verilog; Timing simulation.
Computer-aided design tools that process hardware and architectural representations; Case study.
Case study; Formal verification of digital systems.
Final exam.

Required reading

M. Vučić, G. Molnar (2018.), Alati za razvoj digitalnih sustava - Materijali za predavanja I, FER-ZESOI
M. Vučić, G. Molnar (2009.), Alati za razvoj digitalnih sustava - Materijali za predavanja II, FER-ZESOI
M. Vučić, G. Molnar (2009.), Alati za razvoj digitalnih sustava - Materijali za predavanja III, FER-ZESOI
M. Butorac, G. Molnar, M. Vučić (2015.), Alati za razvoj digitalnih sustava - Upute za praktični rad I,
G. Molnar, M. Vučić (2009.), Alati za razvoj digitalnih sustava - Upute za praktični rad II, FER-ZESOIP. J. Ashenden (2008.), The Designer's Guide to VHDL, Morgan Kaufmann Publishers
P. J. Ashenden (2008.), Digital Design - An Embedded Systems Approach Using VerilogThe Designer's Guide to VHDL, Morgan Kaufmann Publishers
L. H. Crockett, R. A. Elliot, M. A. Enderwitz, R. W. Stewart (2014.), The Zynq Book - Embedded Processing with the ARM Cortex-A9 on the Xilinx Zynq-7000 All Programmable SoC, Strathclyde Academic Media

Minimal learning outcomes

  • Describe system level design
  • Describe the architecture of CPLD, FPGA andSoC circuits
  • Employ a hardware description language (HDL)
  • Develop a digital system using hardware description language
  • Categorize the requirements set on a digital system
  • Assemble digital subsystems into a complete system
  • Analyze the data obtained by testing of digital systems
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